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19-0258; Rev 2; 4/95
UAL IT MAN TION K T VALUA A SHEE E T WS DA FOLLO
8x4 Video Crosspoint Switches with Buffers
_______________General Description
The MAX458/MAX459 are crosspoint switches with eight input channels and four high-speed, buffered output channels. The MAX458 output buffer is configured with a gain of one, while the MAX459 buffer has a gain of two. In each device, any one of eight input lines can be connected to any of four output amplifiers. The output buffers are capable of driving loads of 75. Data interface can be accomplished by either a 16-bit serial or a 6-bit parallel connection. In the serial mode, the MAX458/MAX459 are SPITM, QSPITM, and MicrowireTM compatible. In parallel mode, the MAX458/MAX459 are compatible with most microprocessor buses. Three-state amplifier output capability makes it possible to multiplex MAX458/MAX459s to form larger switch networks. The output buffers can be disabled individually or the entire device can be shut down to conserve power.
____________________________Features
o o o o o o o o o o 100MHz Unity-Gain Bandwidth 300V/s Slew Rate Low 0.05 Differential Phase Error Low 0.01% Differential Gain Error Directly Drives 75 Cables Fast 60ns Switching Time High-Z Amplifier Output Capability Shutdown Capability 16-Bit Serial and 6-Bit Parallel Address Modes 40-Pin DIP and 44-Pin PLCC Packages
MAX458/MAX459
______________Ordering Information
PART MAX458CPL MAX458CQH MAX458EPL MAX459CPL MAX459CQH MAX459EPL TEMP. RANGE 0C to +70C 0C to +70C -40C to +85C 0C to +70C 0C to +70C -40C to +85C PIN-PACKAGE 40 Plastic DIP 44 PLCC 40 Plastic DIP 40 Plastic DIP 44 PLCC 40 Plastic DIP
________________________Applications
Video Test Equipment Video Security Systems Video Editing
_____________________Block Diagram
8 BUFFERED 8x4 4 75 INPUTS SWITCH ARRAY OUTPUT DRIVERS
_________________Pin Configurations
N.C. SCLK
TOP VIEW
GND GND N.C. DIN IN0 CS
6 5 4 3 2 1
UPDATE
WR
MAX459
IN0 75 IN1 75 IN2 75 IN3 75 IN4 75 IN5 75 IN6 75 IN7 75 GND SERIAL OR PARALLEL DIGITAL INTERFACE & CONTROL GND GND GND AV = 2 GND AV = 2 75 GND 75 OUT3 75 GND GND GND 8x4 SWITCH ARRAY GND AV = 2 GND 75 AV = 2 75 GND 75 OUT2 OUT1 75 OUT0 75
44 43 42 41 40
IN1 GND IN2 GND IN3 VCC IN4 VEE IN5 GND IN6
CE
39 GND 38 OUT0 37 GND 36 OUT1 35 VCC 34 OUT2 33 VEE 32 N.C. 31 OUT3 30 GND 29 A0
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MAX458 MAX459
GND
SHDN
DOUT
N.C.
IN7
D3
D2
D1
D0
SERIAL/PARALLEL INTERFACE (SPITM, QSPITM, MICROWIRETM COMPATIBLE)
GND
DIP on last page.
PLCC
TM SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
_______________________________________________________________ Maxim Integrated Products
A1
1
Call toll free 1-800-998-8800 for free samples or literature.
8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (VCC to VEE) .........................................12V Positive Supply Voltage (VCC to GND).....................................6V Negative Supply Voltage (VEE to GND) ...................................6V Analog Input/Output Voltage ...........(VCC + 0.3V) to (VEE - 0.3V) Digital Input Voltage ...................................(VCC + 0.3V) to -0.3V Duration of Output Short Circuit to GND (Note 1) ......Continuous Continuous Power Dissipation Plastic DIP (derate 17mW/C above +70C) ..............1333mW PLCC (derate 13mW/C above +70C) ......................1067mW Operating Temperature Ranges MAX45_C_ _ ........................................................0C to +70C MAX45_E_ _......................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Note 1: Outputs may be shorted to any supply pin or ground as long as package power dissipation ratings are not exceeded.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V, VEE = -5V, -2V VIN +2V, output load resistor (RL) = 150, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER STATIC SPECIFICATIONS Input Voltage Range Input Offset Voltage Input Offset Voltage Match Power-Supply Rejection Ratio On Input Bias Current On Input Resistance Input Capacitance VOS VOS PSRR IIN RIN CIN Any channel VIN = 0V (Note 2) VS = 4.75V to 5.25V VIN = 0V, input programmed to one output Input programmed to one output Input channel on or off MAX458 (Note 3) DC Voltage Gain Accuracy MAX459 (Note 4) Output Voltage Swing Enabled Output Resistance Disabled Output Resistance Disabled Output Capacitance Positive Power-Supply Current Negative Power-Supply Current Positive Supply Current in Shutdown Negative Supply Current in Shutdown Logic Input High Voltage Logic Input Low Voltage 2 VIH VIL (Note 5) (Note 5) 0.8 VOUT ROUT ROUT COUT ICC IEE VIN = 0V, all amplifiers enabled VIN = 0V, all amplifiers enabled TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX 60 50 50 40 VIN = 1kHz sine wave VIN = 10MHz sine wave MAX458 MAX459 TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX 2 0.50 50 TA = +25C TA = TMIN to TMAX 3 60 1 5.0 7 0.1 0.1 3 0.05 4.0 1.0 1.0 12 75 65 0.5 1.0 1.0 2.0 % 5 -2 5 +2 15 20 10 V mV mV dB A M pF SYMBOL CONDITIONS MIN TYP MAX UNITS
V M k pF 85 100 75 90 26 12 2.0 mA mA mA mA V V
0.25 0.70
15 7
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8x4 Video Crosspoint Switches with Buffers
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, VEE = -5V, -2V VIN +2V, output load resistor (RL) = 150, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Logic Input High Current Logic Input Low Current Logic Output High Voltage Logic Output Low Voltage DYNAMIC SPECIFICATIONS Differential Gain Error (Note 6) Differential Phase Error (Note 6) DG DG MAX458 MAX459 MAX458 MAX459 MAX458 Slew Rate SR MAX459 Bandwidth (-3dB) Input Noise Density Settling Time Amplifier Disable Time Amplifier Enable Time Channel Switching Time Channel Switching Propagation Delay Switching Transient Glitch Adjacent Channel Crosstalk Non-Adjacent Channel Crosstalk All-Hostile Crosstalk All-Hostile Off Isolation BW en tS tAOFF tAON tCSW tCPD See Typical Operating Characteristics (Note 8) (Note 9) (Note 10) (Note 11) MAX458, RL = 75 MAX459, RL = 150 f = 10kHz To 0.1% of final value (Note 7) Positive transition Negative transition Positive transition Negative transition 0.01 0.13 0.05 0.14 200 150 300 250 100 90 20 40 100 120 60 50 100 -65 -65 -55 -60 MHz nV/Hz ns ns ns ns ns mVp-p dB dB dB dB V/s % degrees SYMBOL IIH IIL VOH VOL (Note 3) (Note 3) ISOURCE = 400A (Note 5) ISINK = 1.6mA (Note 5) 4.0 0.5 CONDITIONS MIN TYP MAX 10 10 UNITS A A V V
MAX458/MAX459
Note 2: Defined as the DC offset shift when switching between input channels for a given output. Note 3: Voltage Gain Accuracy for MAX458 calculated as (VOUT - VIN) @ (VIN = +2V) - (VOUT - VIN) @ (VIN = -2V) ----------- ------------ -------------------- ---------- ---------- -- -------------------- -- 4V Note 4: Voltage Gain Accuracy for MAX459 calculated as (VOUT/2 - VIN) @ (VIN = +1V) - (VOUT/2 - VIN) @ (VIN = -1V) ------------------------ ---------------------- ---------------------- -- ---------------------- 2V Note 5: All logic levels are guaranteed over the range of VS = 4.75V to 5.25V. Note 6: Differential phase and gain measured with a 40 IRE (285.7mV), 3.58MHz sine wave superimposed on a linear ramp of 0 IRE to 100 IRE (714.3mV). "The IRE scale is a linear scale for measuring, in arbitrary IRE units, the relative amplitudes of the various components of a television signal" (from the "Television Engineering Handbook", edited by K. Blair Benson, McGraw Hill). This system defines 100 IRE as reference white, 0 IRE as the blanking level, and -40 IRE as the sync peak. The equipment used for the test signal generated 714.3mV (100 IRE) as reference white and -285.7mV (-40 IRE) as sync. The modulation used was 285.7mV (40 IRE), which conforms to the EIA color signal standards. Note 7: For MAX458, step input from +2V to 0V; for MAX459, step input from +1V to 0V. All unused channels grounded and all unused amplifiers disabled. Note 8: Test input channel programmed to an output and grounded through a 75 resistor. Adjacent input is programmed to an adjacent output and driven by a 10MHz, 4Vp-p sine wave. Note 9: Same as Note 6 above, except driven input and output are not adjacent to test input/output. Note 10: All inputs but the test input are driven by a 10MHz 4Vp-p sine wave. All outputs except the test output are connected to driven inputs. Note 11: Same as Note 9 above, except with test channel programmed off.
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3
8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
TIMING CHARACTERISTICS (Note 12)
PARAMETER SYMBOL (VCC = +5V, VEE = -5V, -2V VIN +2V, output load resistor (RL) = 150, TA = TMIN to TMAX, unless otherwise noted.) CONDITIONS MIN 20 0 0 0 40 50 0 0 40 25 0 35 50 30 50 0 200 30 20 100 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARALLEL-MODE TIMING (see Figure 1) --- - Address to WR Fall Setup Time tADS --- - Address to WR Rise Hold Time tADH -- -- --- - CE Fall to WR Fall Setup Time tCES -- -- --- - CE Rise to WR Rise Hold Time tCEH --- - WR Pulse Width Low tWR --- - Data to WR Rise Setup Time tDS --- - Data to WR Rise Hold Time tDH --- - - -- --- -- ---- WR Rise to UPDATE Fall Setup Time tWRS - -- --- -- ---- UPDATE Pulse Width Low tUP - -- --- -- ---- --- - UPDATE Rise to WR Fall Setup Time tUPS SERIAL-MODE TIMING (see Figure 6) -- -- SCLK to CS Fall -- -- CS Fall to SCLK Rise SCLK Pulse Width High SCLK Pulse Width Low DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Fall to DOUT -- -- SCLK Rise to CS Rise -- -- CS Rise to SCLK Rise -- -- CS Pulse Width High tCSO tCSS tCH tCL tDS tDH tDO tCSH tCS1 tCSW
Note 12: Timing Characteristics are guaranteed by design.
4
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8x4 Video Crosspoint Switches with Buffers
__________________________________________Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
MAX458/MAX459
POWER SUPPLY CURRENT vs. TEMPERATURE
ICC 80 CURRENT (mA) IEE 60
MAX458/459 Fg TOC1
MAX458 GAIN vs. FREQUENCY
4 2 AMPLITUDE (dB) 0 -2 -4 -6 PHASE 0 36 72 GAIN
MAX458/459 Fg TOC4
MAX459 GAIN vs. FREQUENCY
MAX458/459 Fg TOC5
100
6
GAIN 6 AMPLITUDE (dB) 4 2 0 PHASE PHASE (DEGREES)
PHASE (DEGREES)
0 36 72
40
108 144
108 144 0.1 1 10 180 100 250
20 -60 -40 -20 0 20 40 60 80 100 120 140 0.1 1 10 TEMPERATURE (C) FREQUENCY (MHz)
180 100 250
FREQUENCY (MHz)
CROSSTALK vs. FREQUENCY
MAX458/459 Fg TOC7
OUTPUT IMPEDANCE vs. FREQUENCY
MAX458/459 Fg TOC6
CHANNEL SWITCH TRANSIENT
10V/div (digital) IN2 IN5 IN2 100ns/div UPDATE D1 D0 & D2 20mV/div (analog) OUTPUT 10ns/div INPUT
MAX458/459 Fg TOC9 MAX458/459 Fg TOC3
40
OUTPUT IMPEDANCE ()
0 AMPLITUDE (dB)
10
-40
OUT 1 GND
-80
-120
0.1
0.01
0.1
1 FREQUENCY (MHz)
10
100
1
10 FREQUENCY (MHz)
100
MAX458 LARGE-SIGNAL PULSE RESPONSE
5V
MAX458 SMALL-SIGNAL PULSE RESPONSE
INPUT MAX458/459 Fg TOC8
MAX459 SMALL-SIGNAL PULSE RESPONSE
INPUT
2V/div
+200mV
+200mV -200mV
-200mV GND 1V/div OUTPUT
MAX458/459 Fg TOC2
-100mV
OUTPUT 10ns/div
+100mV
+200mV
-200mV
-15V 25ns/div
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5
8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
______________________________________________________________Pin Description
PIN DIP 1 2, 4, 6, 8, 14, 16, 18, 27, 33, 35 3 5 7 9 10, 31 11 12, 29 13 15 17 19 20 21 22 23 24 25 26 28 30 32 34 36 37 38 39 40 -- PLCC 1 3, 5, 8, 10, 16, 18, 20, 30, 37, 39 4 7 9 11 12, 35 13 14, 33 15 17 19 21 22 23 25 26 27 28 29 31 34 36 38 40 41 42 43 44 2, 6, 24, 32 NAME DIN GND IN0 IN1 IN2 IN3 VCC IN4 VEE IN5 IN6 IN7 SHDN DOUT D3 D2 D1 D0 A1 A0 OUT3 OUT2 OUT1 OUT0 -- -- CE --- - WR - -- --- -- ---- UPDATE SCLK -- -- CS N.C. Serial Data Input Ground Analog Input Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Positive Power Supply (+5V). Connect both VCC pins to the positive supply. Analog Input Channel 4 Negative Power Supply (-5V). Connect both VEE pins to the negative supply. Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Shutdown, active high. Connect to GND if not used. Serial Data Output used for daisy-chaining devices. Parallel Digital Channel Input Address Bit 3 Parallel Digital Channel Input Address Bit 2 Parallel Digital Channel Input Address Bit 1 Parallel Digital Channel Input Address Bit 0 Parallel Digital Amplifier Output Address Bit 1 Parallel Digital Amplifier Output Address Bit 0 Amplifier 3 Analog Output Amplifier 2 Analog Output Amplifier 1 Analog Output Amplifier 0 Analog Output Chip Enable, used in parallel mode. Keep high for serial operation. Write Low, latches input registers in parallel mode. Hold high for serial operation. Update Low, latches amplifier registers in parallel mode. Hold high for serial operation. Serial Clock Chip Select, used in serial operation. Hold high for parallel mode of operation. Not Internally Connected FUNCTION
Note: All GND pins must be grounded for optimum crosstalk performance.
6
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8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
2 IN0 75 4 IN1 75 6 IN2 75 8 IN3 75 34 0.1F VCC IN4 75 10 11 OUT0 ENABLE 33 OUT0 9 35 75 75 7 5 3
MAX458 MAX459
0.1F VEE IN5 75 14 IN6 75 16 IN7 75 18 IN0 32 IN7 OUT1 ENABLE 75 31 30 OUT2 ENABLE OUT2 0.1F VCC 75 75 IN0 IN7 OUT ENABLE 4 OUT3 ENABLE 29 28 27 38 37 36 CE WR UPDATE OUT3 0.1F 75 VEE 75 OUT1 75 17 15 12 13 1 20 39 40 19 DIN DOUT SCLK CS SHDN SERIAL INTERFACE
IN0 IN7
24 D0 PIN NUMBERS APPLY TO DIP PACKAGE.
23 D1
22 D2
21 D3
26
25
A0 A1 PARALLEL INTERFACE
Figure 1. Block Diagram and Typical Operating Circuit
_______________________________________________________________________________________ 7
8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
ANALOG INPUTS IN0 IN7 UPDATE WR CE INPUT REGISTER 1 CONTROL SWITCH REGISTER 1 0 *** OUT0 8-1 MUX ***
7
***
***
INPUT REGISTER 2 CONTROL
SWITCH REGISTER 2
0 8-1 MUX OUT1
7
A0 A1
***
***
INPUT REGISTER 3 CONTROL
SWITCH REGISTER 3
0 8-1 MUX OUT2
7
***
MAX458 MAX459
***
INPUT REGISTER 4 CONTROL D0 D1 D2 D3
SWITCH REGISTER 4
0 8-1 MUX OUT3
7
L = TRANSPARENT H = LATCHED
CS = HIGH, SCLK = DIN = LOW
Figure 2. Parallel-Logic Block Diagram
8 _______________________________________________________________________________________
8x4 Video Crosspoint Switches with Buffers
_______________Detailed Description
Analog Section
The MAX458/MAX459 video crosspoint switches consist of a high-speed 32 (8x4) switch array with wide-bandwidth line drivers (Figure 1). This design allows makebefore-break switching to reduce output noise and glitches, but the inputs will not short together. It also provides high input impedance and low input capacitance, so no input buffer amplifier is needed. However, because different transistors provide gain depending on the input selection, the DC offset voltage shifts slightly when a new input is switched in. The change in offset voltage is typically 3mV. All output buffers will drive back-terminated 50, 75, or higher impedance lines with up to 100pF capacitance. The amplifier outputs can be disabled, which is useful for creating large arrays. When disabled, the MAX458 presents an output impedance of approximately 1M. The MAX459 disabled output impedance is 1k (to ground), due to the internal feedback resistors used to achieve the gain of two. -- -- - -- --- -- ---- During power-on, if CS and UPDATE are held high, all output amplifiers are disabled. In a large array, this feature prevents two ON paralleled amplifiers from distorting each other's signals. The amplifiers can be programmed to come up in any state simultaneously at any time after power-on. See the Creating Large Arrays section.
Digital Section--Parallel Mode
The MAX458/MAX459 have two register banks--an input register and a switch register (Figure 2). Each of these registers is either latched (when the control input is high) or transparent (when the control input- is low). --- - - -- The input register is controlled by WR and CE -- - and is - selected by the decode of A0 and A1. If both WR and -- -- CE are low, the input register selected by A0 and A1 is transparent, and the state of D0-D3 is presented to the switch register. The other three input-- -- - -- registers remain -- --- latched. If D0-D3 change before UPDATE is asserted (goes low), the new data (the changed D0-D3) will then --- - -- -- be latched in the switch register. If WR or CE is high, all input registers are latched and their data is presented
MAX458/MAX459
Table 1. Amplifier Selection
A1 L L H H A0 L H L H Output Amplifier Selected 0 1 2 3
Table 2. Input Selection
D3 L L L L L L D2 L L L L H H H H X D1 L L H H L L H H X D0 L H L H L H L H X Input Channel Selected 0 1 2 3 4 5 6 7 Disable output amplifier selected by A0, A1.
1
DIN
CS SCLK UPDATE WR
40 V CC 39 38 UPDATE 37 WRITE 36 CHIP ENABLE (SELECT) 26
L L H
MAX458 MAX459
CE
Table 3. Writing Data
A0 A1 D0 D1 SHUTDOWN 19 20 SHDN DOUT D2 D3
AMPLIFIER SELECT A0 25 AMPLIFIER SELECT A1 24 DATA BIT D0 23 DATA BIT D1 22 DATA BIT D2 21 DATA BIT D3
Pin numbers apply to DIP package.
Figure 3. Parallel Connection (only logic pins shown)
- - --- - -- -- - -- - ------ CE WR UPDATE FUNCTION H X H Device not selected or is operating in seriX H H al mode. Both registers are latched. Data in input registers passes through H X L switch registers. Output reflects data in X H L input registers. Input register of selected amplifier is transL L H parent. Switch registers are latched. Other input registers are latched. All switch registers and selected input register are transparent. Selected amplifier (choL L L sen by state of A0, A1) reflects input data. Other amplifiers reflect data that had been latched into the input registers previously. 9
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8x4 Video Crosspoint Switches with Buffers
--- - -- -- to their switch registers. As long as either WR or CE is high, the input register will not change. The switch register -- - pass any new data on the falling transition of - -- will -- ---- UPDATE. Each register of the switch-register -- - -- --bank controls the ---- - inputs to one amplifier. With UPDATE low, the switch registers are transparent and switch connection is-- - -- --con---- - trolled by the input register. However, if UPDATE is high, the switch register is latched and any change in data by the input register will not affect the amplifier output state. Two register banks are used so that data can be loaded into input registers without affecting the switch/amplifier selection. This allows amplifiers to be programmed and then changed simultaneously. When the registers are not latched, they are made transparent. Use data bit D3 to disable the amplifier selected by A0-A1 and place its output in high-impedance mode. As an example, the code to disable OUT0 is as follows: Pin Name: D3 D2 D1 D0 A1 A0 Input Code: 1 X X X 0 0 -- - When operating in parallel mode, CS must be wired high and SCLK and DIN should be grounded, as shown in Figure 3. Refer to Figure 4 for the correct timing relationships.
MAX458/MAX459
Digital Section--Serial Mode
The MAX458/MAX459 use a three-wire serial interface that is compatible with SPI, QPSI and Microwire interfaces. -- - -- mode, shown in Figure 5, is enabled Serial -- - - - -- ---- -- -- -- -- when WR, UPDATE, and CE are held high and CS goes low. Figures 6 and 7 show serial-mode timing. Figure 8 shows the MAX458/MAX459 configured for serial operation. Figure 9 shows the Microwire connection, and Figure 10 shows the SPI/QSPI connection. The serial output, DOUT, allows cascading of two or more crosspoint switches to create larger arrays. The data at DOUT is delayed by 16 cycles plus one clock pulse width -at DIN. DOUT changes on SCLK's falling -- - -- -- edge when CS is low. When CS is high, DOUT remains in the state of the last data bit. The MAX458/MAX459 input data in 16-bit blocks. SPI and Microwire interfaces output data in 8-bit blocks, thereby requiring two write cycles to input data. The QSPI interface allows variable word lengths from 8 to 16 bits and can be loaded into the crosspoint in one write cycle. SPI and Microwire limit clock rates to 2MHz, while the QSPI maximum clock rate is 4MHz.
A0/A1 tADS CE tCES WR
ADDRESS VALID tADH
tCEH tWR
tDS D0-D3 DATA VALID
tDH
tUPS
tWRS UPDATE tUP
Figure 4. Parallel-Mode Timing
10
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8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
IN0 DIN CS ONE SHOT IN 0 *** CLK SWITCH REGISTER 0
IN7
***
ANALOG INPUTS CONTROL INPUT
8-1 MUX
OUT0
7
D Q ***
16-BIT SHIFT REGISTER
SWITCH REGISTER 1
***
SCLK
0
8-1 MUX
OUT1
7
***
***
MAX458 MAX459
0 SWITCH REGISTER 2
8-1 MUX
OUT2
7
***
0 Q D OUT SWITCH REGISTER 3 ***
8-1 MUX
OUT3
7
DOUT L = TRANSPARENT H = LATCHED WR = CE = UPDATE = HIGH
Figure 5. Serial-Mode Logic Block Diagram
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11
8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
tCSH CS tCS0 SCLK tDS DIN D0 D3 (OUT3) DOUT D3 DATA FROM PREVIOUS WRITE CYCLE D2 tD0 D2 (OUT3) *** D1 D0 D3 tDH *** D1 (OUT0) D0 (OUT0) tCSS tCH tCL *** *** tCS1 tCSW
Figure 6. Serial-Mode Timing
CS
SCLK
DIN D3 D2 OUT3 DOUT D3 D2 D1 D0 D3 DATA FROM PREVIOUS WRITE CYCLE D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D1 D0 D3 D2 OUT2 D1 D0 D3 D2 OUT1 D1 D0 D3 D2 OUT0 D1 D0
Figure 7. Serial-Mode Data Sequence
1 DIN CS SCLK UPDATE WR 40 39 38 37 36
SERIAL DATA IN
CHIP SELECT SERIAL CLOCK VCC VCC VCC SCLK SK SO I/O SI
MAX458 MAX459
CE
MAX458 MAX459
DIN CS DOUT
MICROWIRE PORT
A0 A1 D0 D1 19 SERIAL DATA OUT 20 SHDN DOUT D2 D3
26 25 24 23 22 21 THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX458/MAX459, BUT MAY BE USED FOR DATA-ECHO PURPOSES.
Pin numbers apply to DIP package.
Figure 8. Serial Connection (only logic pins shown)
12
Figure 9. Microwire Connection
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8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
IN_ SCLK SCK MOSI I/O MOSO CPOL = 0, CPHA = 0 IN_
CS DOUT
THE DOUT-MOSO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX458/MAX459, BUT MAY BE USED FOR DATA-ECHO PURPOSES.
RETURN CURRENT
Figure 10. SPI/QSPI Connection
Figure 11. Low-Crosstalk Layout. Return current from termination resistor does not flow through the ground plane.
__________Applications Information
Grounding and Bypassing, PC Board Layout
As with all analog circuits, good PC board layout, proper grounding, and careful component selection are crucial for realizing the full AC performance of high-speed amplifiers such as the MAX458/MAX459. For optimal performance: 1) Use a large, low-impedance analog ground plane. With multilayer boards, the ground plane(s) should be located on the layer that does not contain signal traces. Connect all GND pins to the analog ground plane. 2) Minimize trace area at the circuit's critical high-impedance nodes to prevent unwanted signal coupling. Surround analog inputs with an AC ground trace (bypassed DC power supply, etc.). The analog input pins of the MAX458/MAX459 have been separated with AC ground pins (GND, VCC, VEE) to minimize parasitic coupling, which can degrade crosstalk. 3) Connect the coaxial-cable shield to the ground side of the 75 terminating resistor at the ground plane to further reduce crosstalk (Figure 11). 4) Bypass all power-supply pins directly to the ground plane with 0.1F ceramic capacitors placed as close to the supply pins as possible. For high-current loads, you may need 10F tantalum or aluminum-electrolytic capacitors in parallel with the 0.1F ceramics. Keep capacitor lead lengths as short as possible to minimize series inductance; surface-mount chip capacitors are ideal.
Creating Larger Arrays
The MAX458/MAX459 assume a high-impedance state on power-up if the inputs are not being programmed to any particular state during that time. They also are in a high-impedance state when disabled. This feature makes it possible to create larger arrays than 8x4 without special programming, other than ensuring that your program doesn't turn on two paralleled outputs simultaneously. Testing has shown no degradation of differential gain or phase when the outputs are connected in parallel. The MAX458/MAX459's input registers remain active during shutdown, which allows the crosspoint to be programmed while the devices are shut down. As a result, all outputs may be simultaneously brought to any state, including disabled. Just program all of the MAX458/ MAX459s into shutdown, and enter the program of your choice by selecting the desired inputs and outputs. Taking SHDN low takes the device(s) out of shutdown. A power-on reset circuit causes the output amplifiers to power up in - -- disabled - - the-- -- mode, whether or not SHDN -- --- -- is applied, if UPDATE and CS are high. The number of MAX458s that can be paralleled is limited by capacitive loading on each output, which must not exceed 100pF. Each input presents approximately 7pF of load, and each output presents approximately 12pF. Therefore, the MAX458/MAX459 will drive a maximum of 14 inputs, or 7 outputs and 2 inputs, or any other combination resulting in less than a 100pF load. Adding isolation resistors enables more MAX458s to be paralleled (see the Driving Capacitive Loads section).
______________________________________________________________________________________
GROUND PLANE
MAX458 MAX459
DIN
SPI/QSPI PORT
RETURN CURRENT
13
8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
Driving Capacitive Loads
When driving loads greater than 100pF, you may need a capacitance compensating resistor in series with the output of each affected amplifier. The required resistor will depend on load as well as capacitance. For 150 or higher load resistances and capacitance up to 1000pF, use a 2.4 resistor. For 100 loads, use a 4.7 resistor. If an output amplifier is loaded with a pure capacitance or with the inputs of other MAX458/MAX459s, the resistors will cause no degradation of gain or other performance because of the high impedance of the crosspoints. However, resistive loads may cause a reduction in gain.
CS SCLK SERIAL DATA INPUT 1 40
MAX458 39 MAX459
28 30 32 OUT3 OUT2 OUT1 OUT0
Daisy-Chaining Devices
The serial output, DOUT, allows cascading of two or more crosspoint switches to create larger arrays. The data at DOUT is the DIN data delayed by 16 cycles plus one clock width. DOUT changes on SCLK's falling -- -- -- - edge when CS is low. When CS is high, DOUT remains in the state of the last data bit. Any number of MAX458/MAX459 crosspoint switches can be daisy-chained by connecting the DOUT of one device to the DIN of the next device in the chain, as shown -- Figure 12. For proper timing, ensure that both in - tCSS (CS low to SCLK high) and tCL are greater than tDO + tDS. DOUT is a TTL-compatible output with an active -- pull- up. It does not become high impedance when CS is high.
DOUT
20
34
DIN
1
40
MAX458 39 MAX459
28 30 32
DOUT
20
34
Figure 12. 16x4 Crosspoint Switch Using Serial "Daisy Chain" Connection
14
______________________________________________________________________________________
8x4 Video Crosspoint Switches with Buffers
____Pin Configurations (continued)
TOP VIEW
DIN 1 GND 2 IN0 3 GND 4 IN1 5 GND 6 IN2 7 GND 8 IN3 9 V CC 10 IN4 11 V EE 12 IN5 13 GND 14 IN6 15 GND 16 IN7 17 GND 18 SHDN 19 DOUT 20 40 CS 39 SCLK 38 UPDATE
MAX458/MAX459
MAX458 MAX459
37 WR 36 CE 35 GND 34 OUT0 33 GND 32 OUT1 31 V CC 30 OUT2 29 V EE 28 OUT3 27 GND 26 A0 25 A1 24 D0 23 D1 22 D2 21 D3
DIP
______________________________________________________________________________________
15
8x4 Video Crosspoint Switches with Buffers MAX458/MAX459
________________________________________________________Package Information
DIM INCHES MAX MIN 0.200 - - 0.015 0.175 0.125 0.080 0.055 0.020 0.016 0.065 0.045 0.012 0.008 2.075 2.025 0.090 0.050 0.625 0.600 0.575 0.525 0.100 BSC 0.600 BSC 0.700 - 0.150 0.120 15 0 MILLIMETERS MIN MAX - 5.08 0.38 - 3.18 4.45 1.40 2.03 0.41 0.51 1.14 1.65 0.20 0.30 51.44 52.71 1.27 2.29 15.24 15.88 13.34 14.61 2.54 BSC 15.24 BSC - 17.78 3.05 3.81 0 15
21-348A
D1
E A2 A D A3 E1
A A1 A2 A3 B B1 C D D1 E E1 e eA eB L
A1 L
e B1 B eA eB
C
40-PIN PLASTIC DUAL-IN-LINE PACKAGE
DIM
A2 C
e
D1 D
B1
D2 B
A A1 A2 A3 B B1 C D D1 D2 D3 e
INCHES MAX MIN 0.180 0.165 0.110 0.100 0.156 0.145 - 0.020 0.021 0.013 0.032 0.026 0.011 0.009 0.695 0.685 0.655 0.650 0.630 0.590 0.500 REF 0.050 REF
MILLIMETERS MIN MAX 4.19 4.57 2.54 2.79 3.68 3.96 0.51 - 0.33 0.53 0.66 0.81 0.23 0.28 17.40 17.65 16.51 16.64 14.99 16.00 12.70 REF 1.27 REF
21-350A
D3 D1 D A1 A
A3
44-PIN PLASTIC LEADED CHIP CARRIER PACKAGE
16
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